For conventional hard disk drive (HDD), the Read Channel usually has several specifications. First, the preamplifier input buffers should output a logic low or “0” when an input signal is less than about 0.682V and should output a logic high or “1” when the input signal is greater than about 1.086V. Additionally, the buffer should be able to tolerate input signals of at least 3.6V. Third, the buffer should be able to operate at speeds up to about 80 MHz, and, fourth, the buffer should use low power when outputting a logic low or “0.”
Turning to FIG. 1, an example of a convention 1.8V input buffer 100 can be seen. Buffer 100 generally comprises PMOS transistors Q1 through Q3, NMOS transistor Q4, and inverter 102. In operation, an input signal VIN is applied to the gates of transistors Q1, Q2, and Q4, and as the input signal VIN is increased, the output signal VOUT remains at logic low or “0” until a an upper voltage (i.e., about 1.086V) is reached. Once reached, the buffer 100 outputs a logic high or “1.” The buffer 100 continues to output a “1” until the input signal decreases to a lower voltage (i.e., about 0.682V) when the buffer 100 switches to a “0.” Effectively, buffer 100 operates like a Schmitt trigger, having hysteresis between the upper voltage and the lower voltage.
There are, however, drawbacks to this configuration. With a supply voltage VCC of about 5V, a nominal threshold for a range between a lower voltage of about 0.682V and an upper voltage of about 1.086V would be about 0.884V. This would necessitate that transistor Q4 have an aspect ratio (channel width to channel length) that is much larger than that of transistors Q2 and Q3. This dramatic difference in aspect ratios may then result in a significant variance in the nominal threshold due at least in part to processes, temperature, and supply voltage variations. Additionally, because the pull-up available from transistors Q1 through Q3 for this configuration is very weak, the switching speed of buffer 100 can be significantly limited (i.e., 20 MHz).
Therefore, there is an need for an improved input buffer.
Some other conventional circuits are: U.S. Pat. No. 7,233,176; U.S. Patent Pre-Grant Publ. No. 2010/0097117; Lee et al., “Mixed-Voltage I/O Buffer Using 0.35 μm CMOS Technology,” Proc. IEEE Int. Conf. Electron., Circuits Syst., August 2008, pp. 850-853; Lee et al., “1.8 V to 5.0 V Mixed-Voltage-Tolerant I/O Buffer With 54.59% Output Duty Cycle,” IEEE International Symposium on VLSI Design, Automation and Test, 2008, April 2008, pp. 93-96; Singh et al., “High-Voltage-Tolerant I/O Buffers With Low-Voltage CMOS Process,” IEEE J. of Solid-State Circuits, Vol. 34, No. 11, November 1999, pp. 1512-1525.